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hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e 4m x 16bit edo dram et part this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0.1/apr.01 description features ? fast access time and cycle time odering information part no trac taa tcac trc thpc hy51v65173hg-45e 45ns 23ns 12ns 74ns 17ns hy51v65173hg-5e 50ns 25ns 13ns 84ns 20ns hy51v65173hg-6e 60ns 30ns 15ns 104ns 25ns 45ns 50ns 60ns active 468mw 432mw 396mw standby 1.8mw(cmos level max) 0.72mw (l-version : max) part number access time package hy51v65173hgj-45 hy51v65173hgj-5 hy51v65173hgj-6 45ns 50ns 60ns 400mil 50pin soj hy51v65173hgt-45e hy51v65173hgt-5e hy51v65173hgt-6e 45ns 50ns 60ns 400mil 50pin tsop-ii preliminary this familiy is a 64mbit dynamic ram organized 4,194,304 x 16bit configuration with extented data out mode cmos drams. extended data out mode is a kind of page mode which is useful for the read opera- tion. the advanced circuit and process allow this device to achieve high performance and low power dissi- pation. features are access time(45ns or 50ns) and refresh cycle(4k ref) and power consumption(normal or low power with self refresh). advanced cmos process as well as circuit techniques for wide operating margins allow this device to achieve high speed access and high reliability ? extended data out operation ? read-modify-write capability ? multi-bit parallel test capability ? lvttl(3.3v) compatible inputs and outputs ? /ras only, cas-before-/ras, hidden and self refresh(l-version) capability ? jedec standard pinout 50pin plastic soj/tsop-ii(400mil) ? single power supply of 3.3v +/- 10% ? battery back up operation(l-version) ? power dissipation ? refresh cycle part no ref normal l-part hy51v65173hg* 4k ref 64ms hy51v65173hgl* 4k ref 128ms * : /ras only, cbr and hidden refresh (s) : self refresh, (l) : low power
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev.0.1/apr.01 2 pin configuration pin function /ras row address strobe /ucas, /lcas column address strobe /we write enable /oe output enable a0-a11 address inputs a0-a11 refresh address inputs i/o 0- i/o 15 data input / output vcc power (3.3v) vss ground nc no connection 1 vcc 2 io0 3 io1 io2 4 5 io3 6 7 12 vcc 13 / we vcc io4 11 nc 10 io7 9 io6 8 io5 14 / ras 15 nc 16 nc nc 17 18 nc 19 20 25 vcc a0 a1 24 a5 23 a4 22 a3 21 a2 50 vss 49 io15 48 io14 io13 47 46 io12 45 44 39 vss 38 / lcas vss io11 40 nc 41 io8 42 io9 43 io10 37 / ucas 36 / oe 35 nc nc 34 33 nc 32 31 26 vss a11 a10 27 a6 28 a7 29 a8 30 a9 50 pin plastic soj / tsop-ii pin description
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev.0.1/apr.01 3 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. recommended dc operating conditions (ta= -30 to 85 o c) note : all voltages are referenced to vss 1. 6.0v at pulse width 10ns which is measured at vcc 2. -0.1v at pulse width 10ns which is measured at vss parameter symbol rating unit ambient temperature t a -30 ~ +85 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v t -0.5 ~ vcc + 0.5 (max 4.6v) v voltage on v cc relative to v ss v cc -0.5 ~ 4.6 v short circuit output current i out 50 ma power dissipation p t 1 w parameter symbol min typ. max unit note power supply voltage v cc 3.0 3.3 3.6 v 1,2 power supply voltage v ss 0 0 0 v 2 input high voltage v ih 2.0 - v cc + 0.3 v 1 input low voltage v il -0.3 - 0.8 v 1
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev.0.1/apr.01 4 dc characteristics (vcc = 3.3v +/- 10%, ta= -30 to 85 c ) note : 1. icc depends on output load condition when the device is selected, icc(max) is specified at the output open condition 2. address can be changed once or less while ras=vil 3. measured with one sequential address change per edo cycle, thpc 4. vih>=vcc-0.2v, 0v<=vil<=0.2v 5. l-version symbol parameter min max unit note voh output level output level voltage(iout= -2ma) 2.4 vcc v vol output level output level voltage(iout=2ma) 0 0.4 v icc1 operating current ( trc = trc min) 45ns - 130 ma 1, 2 50ns - 120 60ns - 110 i cc2 standby current (ttl interface) power supply standby current (/ras, /ucas,/lcas=vih, dout = high-z) - 1 ma icc3 /ras only refresh current (trc= trc min) 45ns - 130 ma 2 50ns - 120 60ns - 110 icc4 extended data out page mode current (/ras=vil, /cas, address cycling : thpc=thpc min) 45ns - 100 ma 1, 3 50ns - 90 60ns - 80 icc5 cmos interface ( /ras, /ucas, /lcas >= vcc-0.2v, dout = high-z) - 0.5 ma standby current ( l-version) - 200 ua 4 icc6 /cas-before-/ras refresh current (trc=trc min) 45ns - 130 ma 50ns - 120 60ns - 110 icc7 battery back up operating current (standby with cbr) (trc=31.25us, tras=300ns, dout=high-z) - 350 ua 4, 5 icc8 standby current (cmos) power supply standby current /ras=vih, /ucas./lcas=vil, dout=enable) - 5 ma 1 icc9 self refresh current (/ras, /ucas, /lcas <=0.2v, dout=high-z) - 350 ua 5 ii(l) input leakage current, any input (0v<= vin<=vcc) -5 5 ua io(l) output leakage current, (dout is disabled, 0v<= vout<=vcc) -5 5 ua
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev.0.1/apr.01 5 capacitance (vcc=3.3v +/-10%, ta=25 c ) note : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. /ras, /ucas and /lcas = v ih to disable d out ac characteristics (vcc=3.3v +/-10%, ta= -30~85c, note 1, 2, 19,20) read, write, read-modify-write and refresh cycles parameter symbol min. max unit note input capacitance (address) ci1 - 5 pf 1 input capacitance (clocks) ci2 - 5 pf 1 output capacitance (data-in, data-out) ci/o - 7 pf 1, 2 parameter symbol -45e -5e -6e unit note min max min max min max random read or write cycle time t rc 74 - 84 - 104 - ns /ras precharge time t rp 25 - 30 - 40 - ns /cas precharge time t cp 7 - 8 - 10 - ns 24 /ras pulse width t ras 45 10,000 50 10,000 60 10,000 ns /cas pulse width t cas 7 10,000 8 10,000 10 10,000 ns row address set-up time t asr 0 - 0 - 0 - ns row address hold time t rah 7 - 8 - 10 - ns column address set-up time t asc 0 - 0 - 0 - ns 21 column address hold time t cah 7 - 8 - 10 - ns 21 /ras to /cas delay time t rcd 11 33 12 37 14 45 ns 3 /ras to column address delay time t rad 9 22 10 25 12 30 ns 4 /ras hold time t rsh 12 - 13 - 15 - ns /cas hold time t csh 38 - 40 - 42 - ns /cas to /ras precharge time t crp 5 - 5 - 5 - ns 22 test condition ? input rise and fall times = 2ns ? input level : v il /v ih = 0.0 / 0.3v ? input timing reference level : v il /v ih = 0.8/2.0v ? output timing reference level : v ol /v oh =0.8/0.2v ? output load : 1 ttl gate + c l (100pf) including scope and jig
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev.0.1/apr.01 6 - continued - read cycles parameter symbol -45e -5e -6e unit note min max min max min max /oe to din delay time t odd 12 - 13 - 15 - ns 5 /oe delay time from din t dzo 0 - 0 - 0 - ns 6 /cas delay time from din tdzc 0 - 0 - 0 - ns 6 transition time ( rise and fall) t t 2 50 2 50 2 50 ns 7 refresh period t ref - 64 - 64 - 64 ms 4k ref. refresh period (l-version) - 128 - 128 - 128 ms 4k ref. parameter symbol -45e -5e -6e unit note min max min max min max access time from /ras t rac - 45 - 50 - 60 ns 8, 9 access time from /cas t cac - 12 - 13 - 15 ns 9,10,17 access time from column address taa - 23 - 25 - 30 ns 9,11,17 access time from /oe t oac - 12 - 13 - 15 ns 9 read command set-up time t rcs 0 - 0 - 0 - ns 21 read command hold time to /cas trch 0 - 0 - 0 - ns 12,22 read command hold time to /ras t rrh 0 - 0 - 0 - ns 12 column address to /ras lead time t ral 23 - 25 - 30 - ns column address to /cas lead time tcal 15 - 15 - 18 - ns output buffer turn off delay time from /cas t off - 12 - 13 - 15 ns 13,26 output buffer turn off delay time from /oe t oez - 12 - 13 - 15 ns 13 /cas to din delay time tcdd 12 - 13 - 15 - ns 5 /ras to din delay time t rdd 12 - 13 - 15 - ns /we to din delay time t wdd 12 - 13 - 15 - ns output buffer turn off delay time from /ras tofr - 12 - 13 - 15 ns 13,26 output buffer turn off delay time from /we t wez - 12 - 13 - 15 ns 13 output data hold time t oh 3 - 3 - 3 - ns 26 output data hold time from /ras tohr 3 - 3 - 3 - ns 26 read command hold time from /ras t rchr 45 - 50 - 60 - ns output data hold time from /oe t oho 3 - 3 - 3 - ns /cas to output in low-z tclz 0 - 0 - 0 - ns
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev.0.1/apr.01 7 write cycles read-modify-write cycles refresh cycles parameter symbol -45e -5e -6e unit note min max min max min max write command set-up time twcs 0 - 0 - 0 - ns 14,21 write command hold time t wch 7 - 8 - 10 - ns 21 write command pulse width twp 7 - 8 - 10 - ns write command to /ras lead time t rwl 12 - 13 - 15 - ns write command to /cas lead time t cwl 7 - 8 - 10 - ns 23 data-in set-up time tds 0 - 0 - 0 - ns 15, 23 data-in hold time tdh 7 - 8 - 10 - ns 15, 23 parameter symbol -45e -5e -6e unit note min max min max min max read-modify-write cycle time trwc 101 - 116 - 140 - ns /ras to /we delay time t rwd 63 - 67 - 79 - ns 14 /cas to /we delay time tcwd 30 - 30 - 34 - ns 14 column address to /we delay time t awd 40 - 42 - 49 - ns 14 /oe hold time from /we t oeh 12 - 13 - 15 - ns parameter symbol -45e -5e -6e unit note min max min max min max /cas set-up time ( /cas-before-/ras refresh cycle) tcsr 5 - 5 - 5 - ns 21 /cas hold time ( /cas-before-/ras refresh cycle) t chr 7 - 8 - 10 - ns 22 /we set-up time ( /cas-before-/ras refresh cycle) twrp 0 - 0 - 0 - ns /we hold time ( /cas-before-/ras refresh cycle) t wrh 7 - 8 - 10 - ns /ras precharge to /cas hold time ( /cas-before-/ras refresh cycle) t rpc 5 - 5 - 5 - ns 21
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev 0.1 / apr. 01 extended data out mode cycles edo page mode read-modify-write cycle self refresh cycle (l-version) parameter symbol -45e -5e -6e unit note min max min max min max edo page mode cyle time thpc 17 - 20 - 25 - ns 25 write pulse width during /cas precharge twpe 7 - 8 - 10 - ns edo mode /ras pulse width trasp - 100k - 100k - 100k ns 16 access time from /cas precharge tacp - 28 - 28 - 35 ns 9,17,22 /ras hold time from /cas precharge trhcp 26 - 28 - 35 - ns /cas hold time referred /oe tcol 7 - 8 - 10 - ns /cas to /oe set-up time tcop 5 - 5 - 5 - ns read command hold time from /cas precharge trchp 26 - 28 - 35 - ns output data hold time from /cas low tdoh 3 - 3 - 3 - ns 9,27 /oe precharge time toep 7 - 8 - 10 - ns parameter symbol -45e -5e -6e unit note min max min max min max edo read-modify-write cycle time thprwc 57 - 57 - 68 - ns edo page mode read-modify-write cycle /cas precharge to /we delay time tcpw 45 - 45 - 54 - ns 14,22 parameter symbol -45e -5e -6e unit note min max min max min max /ras pulse width ( self refresh) trass 100 - 100 - 100 - us 31 /ras precharge time ( self refresh) trps 90 - 90 - 110 - ns 31 /cas hold time ( self refresh) tchs -50 - -50 - -50 - ns 23
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev 0.1 / apr. 01 notes : 1. ac measurements assume t t = 2ns 2. ac initial pause of 200us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing /ras-only refresh or /cas-before-/ras refresh) 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only : if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only : if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t odd or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals, also transition times are measured between v ih (min) and v il (max) 8. assumes that t rcd <=t rcd (max) and t rad <=t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown 9. measured with a load circuit equivalent to 1 ttl loads and 100pf. 10. assumes that t rcd >=t rcd (max) and t rcd + t cac (max) >= t rad + t aa (max) 11. assumes that t rad >=t rad (max) and t rcd + t cac (max) <= t rad + t aa (max) 12. either t rch of t rrh must be satified for a read cycles 13. t off (max), t oez (max), t ofr (max) and t wez (max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels 14 t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only : if t wcs >=t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle : if t rwd >=t rwd (min), t cwd >=t cwd (min), t awd >=t awd (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell : if neither of the above sets of conditions is satified, the condition of the data out (at access time) is indeterminate. 15. t ds and t dh are refered to /ucas and /lcas leading edge in early write cycles and to /we leading edge in delayed write or read-modify-write cycles 16. t rasp defineds /ras pulse width in extended data out mode cycles 17. access time is determined by the longest among t aa , t cac and t acp 18 in delaying write or read-modify-write cycles, /oe must disable output buffer prior to applying data to the device.
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev 0.1 / apr. 01 19. when output buffers are enabled once, sustain the low impedence state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large vcc/vss line noise, which causes to degrade v ih min / v il max level 20. when both /ucas and /lcas go low at the same time, all 16 bit data are written into the device. /ucas and /lcas cannot be staggered within the same write / read cycles 21. t asc , t cah , t rcs , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of /ucas or /lcas 22. t crp , t chr , t rch ,t acp and t cpw are determined by the later rising edge of /ucas or /lcas 23. t cwl , t dh , t ds and t chs should be satified by the both /ucas and /lcas 24. t cp is determined by the time that both /ucas and /lcas are high 25. t hpc (min) can be achieved during a series of edo mode early write cycles or edo mode read cycels if both write and read operation are mixed in a edo mode, /ras cycle[edo mode mix cycle (1)(2)] minimum value of /cas cycle t hpc [t cas + t cp + 2t t ] become greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2) 26. data output turns off and becomes high impedance from later rising edge of /ras and /cas. hold time and turn off time are specified by the timing specifications of later rising edge of /ras and /cas between t ohr and t oh and between t ofr and t off 27. t doh defines the time at which the output level go cross, v ol =0.8v, v oh =2.0v of output timing reference level. 28. before and after self refresh mode, execute cbr refresh to all refresh addresses in or within 64ms period on the condition a) and b) below a) enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b) start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6us after exiting from self refresh mode 29. in case of entering from /ras-only-refresh, it is necessary to execute cbr refresh before and after self refresh mode according as note 28 30. for l-version, it is available to apply each 128ms and 31.2us instead of 64ms and 15.6us at note 28 31. at t rass > 100us, self refresh mode is activated, and not active at t rass < 10us, it is undefined within the range of 10us < t rass < 100us. for t rass > 10us, it is necessary to satify t rps 32. xxx : h or l [ h : v ih (min) <= v in <=v ih (max), l : v ih (min) <=v in <=v ih (max)] ///// : invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il
hy51v65173hgj-45/5/6e hy51v65173hgt-45/5/6e rev.0.1/apr.01 11 package information 400mil 50pin tsop- ii dimension unit: mm 10.16 21.35 max 20.95 min 0.30 0.10 0.80 0.18 max 0.08 min 0.60 max 0.40 min 0.125 0.04 0 ~ 5 deg. 0.145 0.05 1.15 max 0.28 0.08 1.20 max 0.10 11.96 max 11.56 min 0.80 0.68 dimension including the plating thickness base material dimension

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